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data sheet document no. e1864e20 (ver. 2.0) date published april 2013 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2011-2013 specifications ? density: 2g bits ? organization ? 4mbit x 32 i/o x 16 banks ? 8mbit x 16 i/o x 16 banks ? package ? 170-ball fbga ? lead-free (rohs compliant) and halogen-free ? power supply: ? vdd: 1.6v/1.5v 3% and 1.35v 3% ? vddq: 1.6v/1.5v 3% and 1.35v 3% ? data rate: 7.0gbps/6.0gbps (max.) ? 16 internal banks ? four bank groups for tccdl = 3tck ? 8n prefetch architecture: 256 bit per array read or write access for x32; 128 bit for x16 ? burst length (bl): 8 only ? programmable cas latency: 6 to 22 ? programmable write latency: 3 to 7 ? programmable crc read latency: 1 to 3 ? programmable crc write latency: 8 to 14 ? programmable edc hold pattern for cdr ? precharge: auto precha rge option for each burst access ? refresh: auto-refresh, self-refresh ? refresh cycles: 16384 cycles/32ms ? interface: pseudo open drain (pod-15) ? on-die termination (odt): nom. values of 60 or 120 ? pseudo open drain (pod-15) compatible outputs ? 40 pulldown ? 60 pullup ? odt and output driver st rength auto-calibration with external resistor zq pin (120 ) ? programmable termination and driver strength offsets ? selectable external or internal vref for data inputs; programmable offsets for internal vref ? separate external vref for address / command inputs ? operating case temperature range ? tc = 0c to +95c features ? x32/x16 mode configurat ion set at power-up with edc pin ? single ended interface for data, address and command ? quarter data-rate differenti al clock inputs ck_t, ck_c for address and commands ? two half data-rate differential clock inputs wck_t, wck_c, each associated with two data bytes (dq, dbi_n, edc) ? double data rate (ddr) data (wck) ? single data rate (sdr) command (ck) ? double data rate (ddr) addressing (ck) ? write data mask function via address bus (single/double byte mask) ? data bus inversion (dbi) and address bus inversion (abi) ? input/output pll on/off mode ? duty cycle corrector (dcc) for data clock (wck) ? address training: address input monitoring via dq pins ? wck2ck clock training: phase information via edc pins ? data read and write training via read fifo (fifo depth = 6) ? read fifo pattern preload by ldff command ? direct write data load to read fifo by wrtr command ? consecutive read of read fifo by rdtr command ? read/write data transmission integrity secured by cyclic redundancy check (crc?8) ? read/write edc on/off mode ? dq preamble for read on/off mode ? low power modes ? rdqs mode on edc pin ? on-chip temperatur e sensor with read-out ? automatic temperature sens or controlled self-refresh rate ? digital ras lockout ? vendor id, fifo depth and density info fields for identification ? mirror function with mf pin ? boundary scan function with sen pin 2g bits gddr5 sgram edw2032bbbg (64m words x 32 bits)
edw2032bbbg data sheet e1864e20 (ver. 2.0) 2 ordering information part number part number organization (words x bits) vdd, vddq max. data rate package EDW2032BBBG-6A-F edw2032bbbg-7a-f 64m x 32 1.5v / 1.35v 1.6v / 1.35v 6.0gbps / 5.0gbps 7.0gbps / 5.0gbps 170-ball fbga elpida memory density/bank 20: 2gb/16-bank organization 32: x32 power supply, interface b: vdd = 1.6v / 1.5v product family w: gddr5 sgram type d: packaged device e d w 20 32 b b bg - 7a - f revision package bg: fbga speed 6a: 6.0gbps 7a: 7.0gbps environment code f: lead free (rohs compliant) and halogen free
edw2032bbbg data sheet e1864e20 (ver. 2.0) 3 pin configuration
edw2032bbbg data sheet e1864e20 (ver. 2.0) 4 signal function signal function ck_t, ck_c clock zq impedance reference wck01_t, wck01_c, wck23_t, wck23_c data clocks reset_n reset cke_n clock enable mf mirror function cs_n chip select sen scan enable ras_n, cas_n, we_n command inputs vrefc reference voltage for command and address ba0 - ba3 bank address inputs vrefd reference voltage for dq and dbi_n a0 - a12 address inputs vddq i/o power dq0 - dq31 data input/output vssq i/o ground dbi0_n - dbi3_n data bus inversion vdd power supply edc0 - edc3 error detection code vss ground abi_n address bus inversion nc not connected

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edw2032bbbg data sheet e1864e20 (ver. 2.0) 5 1. configuration the elpida gddr5 sgram is a high speed dynamic random-access memory designed for applications requiring high bandwidth. it contains 2,14 7,483,648 bits and is internally configured as a 16-bank dram. the gddr5 sgram uses a 8n prefetch architecture a nd ddr interface to achieve high-speed operation. the device can be configured to operate in x32 mode or x 16 (clamshell) mode. the mode is detected during device initialization. the gddr5 in terface transfers two 32 bit wide data words per wck clo ck cycle to/from the i/o pins. corresponding to the 8n prefetch a singl e write or read access consists of a 256 bit wide, two ck clock cycle data transfer at the internal memory core and eight corresp onding 32 bit wide one-half wck clock cycle data transfers at the i/o pins. the gddr5 sgram operates from a differential clock ck_t and ck_c. commands are registered at every rising edge of ck_t. addresses are registered at every ri sing edge of ck_t and every rising edge of ck_c. gddr5 replaces the pulsed strobes (wdqs & rdqs) used in previous drams such as gddr4 with a free running differential forwarded clock (wck_t, wck_c) with both inpu t and output data registered and driven respectively at both edges of the forwarded wck. read and write accesses to the gddr5 sgram are burst or iented; an access starts at a selected location and continues for a total of eight data words. accesses begin wit h the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command and the next rising ck_c edge are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command and the next ri sing ck_c edge are used to select the bank and the column location for the burst access.
edw2032bbbg data sheet e1864e20 (ver. 2.0) 6 1.1 signal description table 1: signal description signal type detailed function ck_t, ck_c input clock: ck_t and ck_c are differential clock inputs. command inputs are latched on the rising edge of ck_t. address inputs are latched on the rising edge of ck_t and the rising edge of ck_c. all latencies are referenced to ck_t. ck_t and ck_c are externally terminated. wck01_t, wck01_c, wck23_t, wck23_c input data clocks: wck_t and wck_c are differentia l clocks used for write data capture and read data output. wck01_t,wck01_c is asso ciated with dq0-dq15, dbi0_n, dbi1_n, edc0 and edc1. wck23_t,wck23_c is associ ated with dq16-dq31, dbi2_n, dbi3_n, edc2 and edc3. wck clocks operate at nominally twice the ck clock frequency. cke_n input clock enable: cke_n low activates and cke_n high deactivates internal clock, device input buffers and output drivers. taking cke_n hi gh provides precharge power-down and self- refresh operations (all banks idle), or active po wer-down (row active in any bank). cke_n is synchronous for power-down entry and exit and for self-refresh entry. cke_n must be maintained low throughout read and write accesses. input buffers excluding ck_t, ck_c, cke_n, wck01_t, wck01_c, wck23_t, wck23_c are disabled during power-down. input buffers excluding cke_n are disabled during se lf-refresh. the value of cke_n latched at power-up with reset_n going high determines the termination value of the address and command inputs. cs_n input chip select: cs_n low enables, and cs_n high disables the command decoder. all commands are masked when cs_n is registered high, but internal command execution continues. cs_n provides for individual device selection on memory channels with multiple memory devices. cs_n is considered part of the command code. ras_n, cas_n, we_n input command inputs: ras_n, cas_n and we_n (along with cs_n) define the command to be entered. ba0 - ba3 input bank address inputs: ba0-ba3 define to which bank an active, read, write or precharge command is being applied. ba0-ba3 also determine which mode register is accessed with a mode register set command. ba0-ba3 are sampled with the rising edge of ck_t. a0 - a12 input address inputs: a0-a12 provide the row addre ss for active commands. a0-a5(a6) provide the column address and a8 defines the auto precharge function for read and write commands, to select one location out of the memory array in the respective bank. a8 sampled during a precharge command determines whet her the precharge applies to one bank (a8 low, bank selected by ba0-ba3) or all ban ks (a8 high). the address inputs also provide the op-code during an mode register set command, and the data bits during ldff commands. a8-a12 are sampled with the rising edge of ck _t and a0-a7 are sampled with the rising edge of ck_c. dq0 - dq31 i/o data input/output: 32 bit data bus dbi0_n - dbi3_n i/o data bus inversion: dbi0_n is associated wi th dq0-dq7, dbi1_n with dq8-dq15, dbi2_n with dq16-dq23, and dbi3_n with dq24-dq31. edc0 - edc3 output error detection code: the calculated crc data is transmitted on these pins. in addition these pins drive a hold pattern when idle and can be us ed as an rdqs function. edc0 is associated with dq0-dq7, edc1 with dq8-dq15, edc2 with dq16-dq23, and edc3 with dq24-dq31. abi_n input address bus inversion zq - impedance reference: external reference pin for auto-calibration reset_n input reset: vddq cmos input. a full chip reset may be performed at any time by pulling reset_n low. with reset_n low all odts are disabled. mf input mirror function: vddq cmos input. must be tied to power or ground. sen input scan enable: vddq cmos input. must be tied to ground when not in use. vrefc supply reference voltage for command and address inputs. vrefd supply reference voltage for dq and dbi_n inputs. vddq supply isolated power for the input and output buffers. vssq supply isolated ground for the input and output buffers. vdd supply power supply vss supply ground nc - not connected
edw2032bbbg data sheet e1864e20 (ver. 2.0) 7 1.2 mirror function mode the gddr5 sgram provides a mirror f unction (mf) pin to change the physical location of the command, address, data and wck pins assisting in routing devices back to back. the mf ball should be tied directly to vssq or vddq depending on the control line orientation desired. the pins affected by this mirror function mode are listed in table 2 . table 2: ball assignment with mirror function functions within the gddr5 sgram that refer to external signals are transparent with respect to mirror function mode, meaning that the signal names shown in the respective functional description apply both to mirrored (mf=1) and non-mirrored (mf=0) modes. the referenced package pin is determined by the mirror function mode the devices is configured to. 1.3 clamshell mode detection the gddr5 sgram can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a point to point connection on the high speed data signals. the disabled pins in x16 mode will be in hi-z state, non-terminating. the x16 mode is detected at power-up on the pin at location c-13 which is edc1 when configured to mf=0 and edc2 when configured to mf=1. for x16 mode this pin is tied to vssq; the pin is part of the two bytes that are disabled in this mode and therefore not needed for edc f unctionality. for x32 mode this pin is active and always terminated to vddq in the system or by the controller. the configuration is set with reset_n going high. once the configuration has been set, it cannot be changed during normal operation. usually the configuration is fixed in the system. table 3: clamshell mode and mirror function ball signal ball signal ball signal ball signal mf=0 mf=1 mf=0 mf=1 mf=0 mf=1 mf=0 mf=1 a2 dq1 dq25 a4 dq0 dq24 k5 a11 a6 a9 a1 g12 cs_n we_n b2 dq3 dq27 b4 dq2 dq26 p5 wck23_c wck01_c l12 we_n cs_n c2 edc0 edc3 d4 wck01_t wck23_t h10 ba3 a3 ba1 a5 a13 dq9 dq17 d2 dbi0_n dbi3_n e4 dq4 dq28 k10 ba1 a5 ba3 a3 b13 dq11 dq19 e2 dq5 dq29 f4 dq6 dq30 a11 dq8 dq16 c13 edc1 edc2 f2 dq7 dq31 h4 a10 a0 a8 a7 b11 dq10 dq18 d13 dbi1_n dbi2_n m2 dq31 dq7 k4 a8 a7 a10 a0 e11 dq12 dq20 e13 dq13 dq21 n2 dq29 dq5 m4 dq30 dq6 f11 dq14 dq22 f13 dq15 dq23 p2 dbi3_n dbi0_n n4 dq28 dq4 h11 ba0 a2 ba2 a4 m13 dq23 dq15 r2 edc3 edc0 p4 wck23_t wck01_t k11 ba2 a4 ba0 a2 n13 dq21 dq13 t2 dq27 dq3 t4 dq26 dq2 m11 dq22 dq14 p13 dbi2_n dbi1_n u2 dq25 dq1 u4 dq24 dq0 n11 dq20 dq12 r13 edc2 edc1 g3 ras_n cas_n d5 wck01_c wck23_c t11 dq18 dq10 t13 dq19 dq11 l3 cas_n ras_n h5 a9 a1 a11 a6 u11 dq16 dq8 u13 dq17 dq9 mode mf edc1 (mf=0) or edc2 (mf=1) x16 non-mirrored vssq vssq x32 non-mirrored vssq vddq (terminated by the system or controller) x16 mirrored vddq vssq x32 mirrored vddq vddq (terminated by the system or controller)
edw2032bbbg data sheet e1864e20 (ver. 2.0) 8 figure 1 shows examples of the board channels and topologie s that are supported in gddr5 in order to illustrate the expected usage of x16 mode and the mf pin. figure 1: example gddr5 pcb layout topologies *$851'+*010'%/$7*89:4!*/$+ -'( -'( -'( -'( -'( -'( -'( -'( -'( -'( -'( -'( -'( -'( 54.+=155'%/$7*89:4!*/$+ -'( -'( -'( -'( -'( -'(

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edw2032bbbg data sheet e1864e20 (ver. 2.0) 9 1.4 clocking the gddr5 sgram operates from a differential clock ck_t and ck_c. commands are registered at every rising edge of ck_t. addresses are registered at every ri sing edge of ck_t and every rising edge of ck_c. gddr5 uses a double data rate data interface and an 8n-prefetch architecture. the data interface uses two differential forwarded clocks (wck_t, wck_c). ddr means that the data is registered at every rising edge of wck_t and rising edge of wck_c. wck_t and wck_c are continu ously running and operate at twice the frequency of the command/address clock (ck_t, ck_c). figure 2: gddr5 clocking and interface relationship 1.5 addressing the gddr5 sgram uses a double data rate address schem e to reduce pins required on the gddr5 sgram as shown in table 4 . the addresses should be provided to the gddr5 sgram in two parts; the fi rst half is latched on the rising edge of ck_t along with the command pins such as ras_n, cas_n and we_n; the second half is latched on the rising edge of ck_c. the use of ddr addressing allows all address values to be latched in at the same rate as the sdr commands. all addresses related to command access have been positioned for latching on the initial rising edge for faster decoding. table 4: address pairs addressing schemes for x32 mode and x16 mode differ only in the number of valid colu mn addresses, as shown in table 5 . table 5: addressing scheme clock edge address inputs rising ck_t ba3 ba2 ba1 ba0 a12 a11 a10 a9 a8 rising ck_c a3 a4 a5 a2 (rfu) a6 a0 a1 a7 64m x 32 128m x 16 row address a0-a12 a0-a12 column address a0-a5 a0-a6 bank address ba0-ba3 ba0-ba3 autoprecharge a8 a8 page size 2 kb 2 kb refresh 16k/32ms 16k/32ms refresh period 1.9 s 1.9 s #' ( )
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edw2032bbbg data sheet e1864e20 (ver. 2.0) 10 1.6 commands table 6: command truth table notes: 1. h = logic high level; l = logic low level; x = don?t care. signal may be h or l, but not floating. 2. addresses shown are logical addresses; physical addres ses are inverted when address bus inversion (abi) is activated and abi_n=l. 3. ba0-ba3 provide the mode register address (mra), a0-a11 the opcode to be loaded. 4. ba0-ba3 provide the bank address (ba), a0-a12 provide the row address (ra). 5. ba0-ba3 provide the bank address, a0-a5 (a6) provide th e column address (ca); no sub-word addressing within a burst of 8. 6. this command is refresh when cke_n(n) = l, and self-refresh entry when cke_n(n) is h. 7. ba0-ba2 select burst location (bst) and a0-a9, ba3 provide the data. 8. deselect and no operation are functionally interchangeable. 9. in address training mode read is decoded from the comm and pins only with ras_n = h, cas_n = l, we_n= h. operation code cke_n (n-1) cke_n (n) cs _n ras _n cas _n we _n ba3- ba0 a12 a11 a10 a8 a6-a7, a9 a0-a5 (a6) note deselect desel l x h x x x x x x x x x x 2,8 no operation (nop) nop l x lhhhxxxxxx x 2,8 mode register set mrs l l l l l l mra x opcode 2,3 activate act l l l l h h ba ra 2,4 read rd l l l h l h ba x l l l x ca 2,5,9 read with autoprecharge rda l l l h l h ba x l l h x ca 2,5 load fifo ldff l l l h l h bst x h l l data 2,7 read training rdtr l l l h l h x x h h l x x 2 write without mask wr l l l h l l ba x l l l x ca 2,5 write without mask with autoprecharge wra l l l h l l ba x l l h x ca 2,5 write with single byte mask wsm l l l h l l ba x l h l x ca 2,5 write with autoprecharge, single byte mask wsma l l l h l l ba x l h h x ca 2,5 write with double byte mask wdm l l l h l l ba x h l l x ca 2,5 write with autoprecharge, double byte mask wdmal l lh l lbax hlhx ca 2,5 write training wrtr l l l h l l x x h h l x x 2 precharge pre l l l l h l ba x x x l x x 2 precharge all preall l l l l h l x x x x h x x 2 refresh ref l l l l l h x x x x x x x 6 power-down entry pde l h h x x x xxxxxx x lhhh power-down exit pdx h l h x x x xxxxxx x lhhh self refresh entry sre l h ll l hxxxxxx x 6 self refresh exit srx h l h x x x xxxxxx x lhhh
edw2032bbbg data sheet e1864e20 (ver. 2.0) 11 2. electrical characteristics table 7: absolute maximum ratings caution: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage of the device. this is a stress rating only , and functional operation of the device at these or any other conditions above those indicated in the operational sections of these specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.1 operating conditions table 8: operating temperature range notes: 1. operating temperature tc is the case surface temper ature on the center / top side of the dram. it specifies the temperature where all dram specifications will be supported. 2. for measurement conditions, pleas e refer to jedec document jesd51-2. table 9: input capacitance notes: 1. the capacitance is measured according to jep147 (?procedure for measuring input capacitance using a vector network analyzer (vna)?) with vdd, vddq, vss, vssq applied and all other pins floating (except the pin under test). vdd=vddq=1.5v and on-die termination off. 2. dcio = cio.max - cio.min 3. dci1 = ci1.max - ci1.min 4. dci2 = absolute value of c ck_t - c ck_c 5. dci3 = absolute value of c wck_t - c wck_c 6. dci1 and ci1 apply to ras_n, cas_n, we_n, cs_n, cke_n, abi_n, ba3/a3, ba2/a4, ba1/a5, ba0/a2, a12/rfu, a11/a6, a10/a0, a9/a1, a8/a7 parameter symbol min. max. unit voltage on vdd supply relative to vss vdd -0.5 2.0 v voltage on vddq supply relative to vssq vddq -0.5 2.0 v voltage on vref and inputs relative to vss vin -0.5 2.0 v voltage on i/o pins relative to vss vout -0.5 2.0 v storage temperature tstg -55 +150 c short circuit output current iout ? 50 ma parameter symbol min max unit operating temperature tc 0 +95 c parameter symbol min max unit notes delta input/output capacitance: dq, dbi_n, edc dcio ? 0.3 pf 1,2 delta input capacitance: command and address dci1 ? 0.2 pf 1,3,6 delta input capacitance: ck_t, ck_c dci2 ? 0.1 pf 1,4 delta input capacitance: wck_t, wck_c dci3 ? 0.1 pf 1,5 input/output capacitance: dq, dbi_n, edc cio 1.0 1.5 pf 1 input capacitance: command and address ci1 1.3 1.5 pf 1,6 input capacitance: ck_t, ck_c ci2 1.4 1.6 pf 1 input capacitance: wck_t, wck_c ci3 0.9 1.1 pf 1
edw2032bbbg data sheet e1864e20 (ver. 2.0) 12 gddr5 sgrams are designed for 1.5v typical voltage supplies. this gddr5 sgram does also support 1.35v typical voltage supplies. the interfac e of gddr5 with 1.5v vddq will follo w the pod15 specification (jesd8-20a). the interface of gddr5 with 1.35v vddq will follow the pod135 specification class b (jesd8-21). i/o levels are given here for reference only. all ac and dc values are measured at the ball. table 10: dc operating conditions notes: 1. gddr5 sgrams are designed to tolerate pcb designs with separate vddq and vdd power regulators. 2. ac noise in the system is estimated at 50 mv peak-to-peak for the purpose of dram design. 3. source of reference voltage and control of reference vo ltage for dq and dbi_n pins is determined by vrefd, half vrefd and vrefd offset mode registers. 4. vrefd offsets are not supported with vrefd2. 5. external vrefc is to be provided by the controller as there is no alternative supply. 6. db, dbi_n input slew rate must be greater than or equal to 3v/ns for pod15 and 2.7v/ns for pod135. the slew rate is measured between vrefd crossing and vihd(ac) or vild(ac) or vrefd2 crossing and vihd2(ac) or vild2(ac). 7. add/cmd input slew rate must be greater than or equal to 3v/ns for pod15 and 2.7v/ns for pod135. the slew rate is measured between vrefc crossing and viha(ac) or vila(ac). parameter symbol pod15 pod135 unit notes min. typ. max. min. typ. max. device supply voltage (-7a) vdd 1.552 1.6 1.648 1.3095 1.35 1.3905 v 1 device supply voltage (-6a) vdd 1.455 1.5 1.545 1.3095 1.35 1.3905 v 1 i/o supply voltage (-7a) vddq 1.552 1.6 1.648 1.3095 1.35 1.3905 v 1 i/o supply voltage (-6a) vddq 1.455 1.5 1.545 1.3095 1.35 1.3905 v 1 reference voltage for dq and dbi_n pins vrefd 0.69 * vddq ? 0.71 * vddq 0.69 * vddq ? 0.71 * vddq v2,3 reference voltage for dq and dbi_n pins vrefd2 0.49 * vddq ? 0.51 * vddq 0.49 * vddq ? 0.51 * vddq v2,3,4 external reference voltage for address and command vrefc 0.69 * vddq ? 0.71 * vddq 0.69 * vddq ? 0.71 * vddq v5 dc input logic high voltage for address and command inputs viha(dc) vrefc + 0.15 ?? vrefc + 0.135 ??v dc input logic low voltage for address and command inputs vila(dc) ? ? vrefc - 0.15 ?? vrefc - 0.135 v dc input logic high voltage for dq, dbi_n inputs with vrefd vihd(dc) vrefd + 0.10 ?? vrefd + 0.09 ??v dc input logic low voltage for dq, dbi_n inputs with vrefd vild(dc) ? ? vrefd - 0.10 ?? vrefd - 0.09 v dc input logic high voltage for dq, dbi_n inputs with vrefd2 vihd2(dc) vrefd2 + 0.30 ?? vrefd2 + 0.27 ??v dc input logic low voltage for dq, dbi_n inputs with vrefd2 vild2(dc) ? ? vrefd2 - 0.30 ?? vrefd2 - 0.27 v input logic high voltage for reset_n, sen, mf vihr vddq - 0.5 ?? vddq - 0.5 ??v input logic low voltage for reset_n, sen, mf vilr ? ? 0.3 ? ? 0.3 v input logic high voltage for edc1/2 (x16 mode detect) vihx vddq - 0.3 ?? vddq - 0.3 ??v8 input logic low voltage for edc1/2 (x16 mode detect) vilx ? ? 0.3 ? ? 0.3 v 8 input leakage current (any input 0v vin vddq; all other pins not under test = 0v) il -5 ? +5 -5 ? +5 a 9 output leakage current (dqs are disabled; 0v vout vddq) ioz -5 ? +5 -5 ? +5 a 10 output logic low voltage vol(dc) ? ? 0.62 ? ? 0.56 v external resistor value zq 115 120 125 115 120 125
edw2032bbbg data sheet e1864e20 (ver. 2.0) 13 8. vihx and vilx define the input voltage levels for the receiver that detects x32 mode or x16 mode with reset_n going high. 9. il is measured with odt off. any input 0v vin vddq; all other pins not under test = 0v. 10. ioz is measured with dqs disabled; 0v vout vddq. table 11: ac operating conditions notes: 1. for optimum performance it is recommended that signal swings are larger than shown in the table. table 12: clock input operating conditions notes: 1. this provides a minimum of 0.9v to a maximum of 1.2v, and is nominally 70% of vddq with pod15. if pod135, this provides a minimum of 0.845v to a maximum of 1.045v, and is nominally 70% of vddq. dra m timings relative to ck cannot be guaranteed if these limits are exceeded. 2. for ac operations, all dc clock requi rements must be satisfied as well. 3. the value of vixck and vixwck is expected to equal 70% vddq for the transmitting devic e and must track variations in the dc level of the same. 4. vidck is the magnitude of the difference between the i nput level in ck_t and the input level on ck_c. the input reference level for signals other than ck_t and ck_c is vrefc. 5. vidwck is the magnitude of the difference between the input level in wck_t and the input level on wck_c. the input reference level for signals other than wck_t and wck_c is either vrefd, vrefd2 or the internal vrefd. 6. the ck_t and ck_c input reference level (for timing refe renced to ck_t and ck_c) is the point at which ck_t and ck_c cross. please refer to the applic able timings in the ac timings table. 7. the wck_t and wck_c input reference level (for timing referenced to wck_t and wck_c) is the point at which wck_t and wck_c cross. please refer to the applicable timings in the ac timings table. 8. vrefd is either vrefd, vrefd2 or the internal vrefd. 9. the slew rate is measured between vrefc crossing and vixck(ac). 10. the slew rate is measured be tween vrefd crossing and vixwck(ac). parameter symbol pod15 pod135 unit notes min. typ. max. min. typ. max. ac input logic high voltage for address and command inputs viha(ac) vrefc + 0.20 ?? vrefc + 0.18 ??v ac input logic low voltage for address and command inputs vila(ac) ? ? vrefc - 0.20 ?? vrefc - 0.18 v ac input logic high voltage for dq, dbi_n inputs with vrefd vihd(ac) vrefd + 0.15 ?? vrefd + 0.135 ??v ac input logic low voltage for dq, dbi_n inputs with vrefd vild(ac) ? ? vrefd - 0.15 ?? vrefd - 0.135 v ac input logic high voltage for dq, dbi_n inputs with vrefd2 vihd2(ac) vrefd2 + 0.40 ?? vrefd2 + 0.36 ??v ac input logic low voltage for dq, dbi_n inputs with vrefd2 vild2(ac) ? ? vrefd2 - 0.40 ?? vrefd2 - 0.36 v parameter symbol pod15 pod135 unit notes min. max. min. max. clock input mid-point voltage: ck_t, ck_c vmp(dc) vrefc - 0.1 vrefc + 0.1 vrefc - 0.1 vrefc + 0.1 v1,6 clock input differential voltage: ck_t, ck_c vidck(dc) 0.22 ? 0.198 ? v 4,6 clock input differential voltage: ck_t, ck_c vidck(ac) 0.40 ? 0.36 ? v 2,4,6 clock input differential voltage: wck_t, wck_c vidwck(dc) 0.20 ? 0.18 ? v 5,7 clock input differential voltage: wck_t, wck_c vidwck(ac) 0.30 ? 0.27 ? v 2,5,7 clock input voltage level for ck_t, ck_c, wck_t, wck_c single ended inputs vin -0.3 vddq + 0.3 -0.3 vddq + 0.3 v ck_t, ck_c single ended slew rate ckslew 3 ? 2.7 ? v/ns 9 wck_t, wck_c single ended slew rate wckslew 3 ? 2.7 ? v/ns 10 clock input crossing point voltage: ck_t, ck_c vixck(ac) vrefc - 0.12 vrefc + 0.12 vrefc - 0.108 vrefc + 0.108 v2,3,6 clock input crossing point voltage: wck_t, wck_c vixwck(ac) vrefd - 0.10 vrefd + 0.10 vrefd - 0.09 vrefd + 0.09 v 2,3,7, 8
edw2032bbbg data sheet e1864e20 (ver. 2.0) 14 3. package drawing 170-ball fbga solder ball: lead free (sn-ag-cu) eca-ts2-0327-02 a unit: mm 0.12 s 0.2 s 1.1 0.1 0.35 0.05 s s 12.0 0.1 index mark 14.0 0.1 0.2 s a index mark 170- 0.45 0.05 b 0.8 0.15 m s 12.8 ab 2.0 10.4 0.8 0.2 s b
edw2032bbbg data sheet e1864e20 (ver. 2.0) 15 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
edw2032bbbg data sheet e1864e20 (ver. 2.0) 16 m01e1007 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, this product is not intended for use in the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. customers are instructed to contact elpida memory's sales office before using this product for such applications. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air, cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.
edw2032bbbg data sheet e1864e20 (ver. 2.0) 17 revision history ver. date description 1.0 dec. 2011 initial version 2.0 apr. 2013 speed bins ?40? and ?50? deleted; table ?input capacitance? added (p11)

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